In verification of logic circuits, RTL (Register Transfer Level) simulation by software is frequently used. However, if the target circuit is a large size logic circuit, sufficient verification may not be achieved with RTL simulation because of its low simulation speed. Hence, a logic circuit emulator, in which a logic circuit is configured on an FPGA (Field Programmable Gate Array) and run in this state in operation, is in use.
However, if a logic circuit of an extremely large size is a target, the circuit may not be contained in a single FPGA. In such case, a logic circuit emulator including a plurality of sub-systems (FPGA or emulator boards) may be used. That is, such a method is used in which the logic circuit is partitioned into a plurality of sub-circuits each of which is allocated to one of the sub-systems.
In partitioning a logic circuit as verification target, referred to below as a “verification target circuit,” into a plurality of sub-circuits, a circuit partitioning tool provided by CAD (Computer Aided Design) vendor, for example, may be used. Initially, a designer enters the verification target circuit into the circuit partitioning tool, and specifies which portion of the verification target circuit is to be allocated to which one of the multiple sub-circuits. The circuit partitioning tool then estimates the circuit size of each sub-circuit. The verification target circuit is then partitioned into a plurality of sub-circuits so that each partitioned portion of the verification target circuit will be of a size loadable on each sub-system of the logic circuit emulator. These sub-circuits are then loaded on the sub-systems of the logic circuit emulator. Any large sized logic circuits may be verified in this manner by the logic circuit emulator.
In the logic circuit emulator in which the verification target circuit is so partitioned and mounted, limitations are imposed on the number of signal lines between the different sub-systems. Thus, in an emulation system, which makes use of time-multiplexed interconnections, as disclosed in Patent Literature 1, a method of time-multiplexing signals between the different sub-systems is used. In the virtual interconnections for a reconfigurable logic system, as disclosed in Patent Literature 2, a similar method of time-multiplexing signals between the sub-systems is used.
FIG. 16 depicts a block diagram showing the configuration of the emulation system which makes use of the time-multiplexed interconnections disclosed in Patent Literature 1. FIG. 17 depicts a waveform diagram for illustrating an operation of the emulation system which makes use of the time-multiplexed interconnections disclosed in Patent Literature 1.
FIG. 18 depicts a block diagram showing the configuration of virtual interconnections for the reconfigurable logic system disclosed in Patent Literature 2. FIG. 19 depicts a waveform diagram for illustrating an operation of the virtual interconnections for the reconfigurable logic system disclosed in Patent Literature 2.
Referring to FIGS. 17 and 19, the Patent Literatures 1 and 2 use a signal transfer clock which is higher in speed than the emulation clock. Signals are transferred between the different sub-systems at a transfer speed faster than that of the emulation clock to overcome the problem of limitations on the number of signal lines between the different sub-systems.